The present invention relates, in general, to the field of integrated circuit ("IC") memory devices. More particularly, the present invention relates to a memory cell array architecture and simultaneous multiple cell refresh technique of especial utility in conjunction with integrated circuit "system on-chip" designs requiring intermediate size memory arrays.
Dynamic random access memory ("DRAM") devices are designed utilizing a volatile, dynamic memory cell architecture, with each cell comprising a single transistor and capacitor. They are "volatile" in the sense that upon powerdown, the memory contents are lost and "dynamic" in the sense that they must be constantly refreshed to maintain the charge in the cell capacitor. The refresh operation is accomplished when the memory contents of a row of cells in the memory array are read by the sense amplifiers and the logic states in the cells that have been read are amplified and written back to the cells. DRAM are used primarily for memory reads and writes and are relatively inexpensive to produce in terms of die area. It does, however, provide relatively slow access times.
On the other hand, static random access memory ("SRAM") devices are designed utilizing a volatile static memory cell architecture. They are considered to be "static" in that the contents of the memory cells need not be refreshed and the memory contents may be maintained indefinitely as long as power is supplied to the device. The individual memory cells of an SRAM comprise a simple, bi-stable transistor-based latch, using four or six transistors, that is either set or reset depending on the state of the data that was written to it. SRAMs provide much faster read and write access time than DRAM and are generally used as a memory cache. However, because the individual memory cell size is significantly larger, they are much more expensive to produce in terms of on-chip die area than DRAMs and they also generate more heat. Typical devices cost three to four times that of DRAMs.
Pseudo SRAMs ("PSRAMs") have, like DRAMs volatile, dynamic memory architecture that utilizes a similar single transistor/single capacitor memory cell architecture, and must be periodically refreshed. However, the primary difference is that it incorporates on-chip refresh timing and control logic to simplify and minimize external logic. They are designed to be pin-for-pin compatible with SRAM devices but are not a direct "drop-in" replacement due to the fact that the memory must be periodically refreshed.
Typical integrated "system on chip" circuits require relatively large embedded memories. For relatively small memory size requirements, SRAMs are generally used since the penalty in die area per bit to be stored is relatively minor. On the other hand, for large memory requirements, DRAM arrays are generally used due to their use of the smaller size, single transistor/single capacitor memory cell. However, the design of an embedded memory is more complex than that of SRAMs and may require a number of undesired, DRAM specific process steps in fabricating the overall integrated circuit "system on chip".
For intermediate size memory requirements, a four transistor ("4T") per bit DRAM cell may be used. Although sometimes referred to as pseudo SRAM, or pseudo DRAM, they are, nevertheless, dynamic, and the advantage of such a cell is that the layout and design (and hence, processing) is as simple and straightforward as that of a four transistor SRAM cell. Moreover, they can be made with a much smaller feature size. A significant drawback to conventional 4T designs is the frequency with which they must be periodically refreshed, and that rate becomes ever higher as the device geometry is decreased to further increase IC integration. The refresh rate for such a memory cell design can then become a significant input/output ("I/O")"bottleneck", especially when the memory bandwidth requirements are high. As a consequence, a need exists for an intermediate size memory architecture with a reduced refresh rate requirement.